1. Field of the Invention
The present invention relates to a CMOS type solid-state imaging device and an electronic apparatus including the solid-state imaging device, which is applicable to, for example, a camera or the like.
2. Description of the Related Art
As a solid-state imaging device, a CMOS solid-state imaging device is known. Since the CMOS solid-state imaging device has a low power supply voltage and low power consumption, the CMOS solid-state imaging device is used in digital still cameras, digital video cameras, various mobile terminals such as a mobile phone including a camera therein, printers, and the like.
In the CMOS solid-state imaging device, a pixel arranged in a pixel region includes a plurality of pixel transistors in addition to photodiodes PD which are photoelectric conversion portions, unlike a CCD solid-state imaging device. In a general unit pixel, the pixel transistor includes four transistors, namely, a transfer transistor including a floating diffusion portion FD which is a voltage conversion portion, a reset transistor, an amplification transistor and a selection transistor. Alternatively, the pixel transistor includes three transistors, namely, a transfer transistor, a reset transistor and an amplification transistor omitting the selection transistor. Since the photodiodes and the plurality of pixel transistors are necessary as the unit pixel, it is difficult to reduce the size of the pixels.
However, recently, a technology necessarily including a so-called multi-pixel shared structure of sharing the pixel transistors among a plurality of pixels so as to suppress the size of an area occupied by one pixel other than the photodiode PD is used. FIG. 29 shows an example of a solid-state imaging device in which shared pixels are two-dimensionally arranged by the multi-pixel shared structure described in Japanese Unexamined Patent Application Publication No. 2006-54276. The solid-state imaging device 91 is a four-pixel shared example in which photodiodes PD are arranged in a zigzag. In the solid-state imaging device 91, sets of two obliquely neighboring photodiodes PD sharing one floating diffusion portion FD are two-dimensionally arranged. The shared pixels include four photodiodes PD1 to PD4 arranged in a zigzag by two sets neighboring in a vertical direction and two circuit groups (pixel transistors) in pixel transistor forming regions 114 divided at upper and lower positions of one set.
Transfer gate electrodes TG [TG1 to TG4] are formed between the floating diffusion portions FD and two photodiodes PD sandwiching the floating diffusion portions FD therebetween of two sets. In the shared pixels, the two sets are electrically connected to the two circuit groups in the pixel transistor regions 94 through a connection wiring 92 so as to share the four photodiodes PD1 to PD4 in the vertical direction. That is, the floating diffusion portions FD1 and FD2, a gate electrode (not shown) of the amplification transistor and a source (not shown) of the reset transistor are connected by the connection wiring 92 (so-called FD wiring) along the vertical direction.
The related art of the CMOS solid-state imaging device are disclosed in Japanese Unexamined Patent Application Publication Nos. 2004-172950, 2005-157953, 2009-135319, 2003-31785, and 2005-223860.
In the Japanese Unexamined Patent Application Publication Nos. 2004-172950 and 2005-157953, a CMOS solid-state imaging device in which two pixels are shared is disclosed.
In the Japanese Unexamined Patent Application Publication No. 2009-135319, a CMOS solid-state imaging device in which two pixels located in a vertical direction and two pixels located in a horizontal direction, namely, a total of four pixels are shared.
In the Japanese Unexamined Patent Application Publication No. 2003-31785, a back-illuminated type CMOS solid-state imaging device is disclosed.
In the Japanese Unexamined Patent Application Publication No. 2003-31785, a CMOS solid-state imaging device for performing vertical stripe correction is disclosed.